Laser and plasma etch wafer dicing with partial pre-curing of uv release dicing tape for film frame wafer application

ABSTRACT

Methods and systems of laser and plasma etch wafer dicing using UV-curable adhesive films. A method includes forming a mask covering ICs formed on the wafer. The semiconductor wafer is coupled to a film frame by a UV-curable adhesive film. A pre-cure of the UV-curable adhesive film cures a peripheral portion of the adhesive extending beyond an edge of the wafer to improve the exposed adhesive material&#39;s resistance to plasma etch and reduce hydrocarbon redeposition within the etch chamber. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the ICs. A center portion of the UV-curable adhesive is then cured and the singulated ICs detached from the film.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority to U.S. ProvisionalApplication No. 61/715,190 filed on Oct. 17, 2012, titled “LASER ANDPLASMA ETCH WAFER DICING WITH PARTIAL PRE-CURING OF UV RELEASE DICINGTAPE FOR FILM FRAME WAFER APPLICATION,” the entire contents of which ishereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

Embodiments of the present invention pertain to the field ofsemiconductor processing and, in particular, to methods of dicingsemiconductor wafers, each wafer having a plurality of integratedcircuits thereon.

DESCRIPTION OF RELATED ART

In semiconductor wafer processing, integrated circuits are formed on awafer (also referred to as a substrate) composed of silicon or othersemiconductor material. In general, layers of various materials whichare either semiconducting, conducting, or insulating are utilized toform the integrated circuits. These materials are deposited and etchedusing various well-known processes to form integrated circuits. Eachwafer is processed to form a large number of individual regionscontaining integrated circuits known as dice.

Following the integrated circuit formation process, the wafer is “diced”to separate the individual die from one another for packaging or for usein an unpackaged form within larger circuits. The two main techniquesthat are used for wafer dicing are scribing and sawing. With scribing, adiamond tipped scribe is moved across the wafer surface along pre-formedscribe lines. These scribe lines extend along the spaces between thedice. These spaces are commonly referred to as “streets.” The diamondscribe forms shallow scratches in the wafer surface along the streets.Upon the application of pressure, such as with a roller, the waferseparates along the scribe lines. The breaks in the wafer follow thecrystal lattice structure of the wafer substrate. Scribing can be usedfor wafers that are about 10 mils (thousandths of an inch) or less inthickness. For thicker wafers, sawing is presently the preferred methodfor dicing.

With sawing, a diamond tipped saw rotating at high revolutions perminute contacts the wafer surface and saws the wafer along the streets.The wafer is mounted on a supporting member such as an adhesive filmstretched across a film frame and the saw is repeatedly applied to boththe vertical and horizontal streets. One problem with either scribing orsawing is that chips and gouges can form along the severed edges of thedice. In addition, cracks can form and propagate from the edges of thedice into the substrate and render the integrated circuit inoperative.Chipping and cracking are particularly a problem with scribing becauseonly one side of a square or rectangular die can be scribed in thedirection of the crystalline structure. Consequently, cleaving of theother side of the die results in a jagged separation line. Because ofchipping and cracking, additional spacing is required between the diceon the wafer to prevent damage to the integrated circuits, e.g., thechips and cracks are maintained at a distance from the actual integratedcircuits. As a result of the spacing requirements, not as many dice canbe formed on a standard sized wafer and wafer real estate that couldotherwise be used for circuitry is wasted. The use of a saw exacerbatesthe waste of real estate on a semiconductor wafer. The blade of the sawis approximately 15 microns thick. As such, to insure that cracking andother damage surrounding the cut made by the saw does not harm theintegrated circuits, three hundred to five hundred microns often mustseparate the circuitry of each of the dice. Furthermore, after cutting,each die requires substantial cleaning to remove particles and othercontaminants that result from the sawing process.

Plasma dicing has also been used, but may have limitations as well. Forexample, one limitation hampering implementation of plasma dicing may becost. A standard lithography operation for patterning resist may renderimplementation cost prohibitive. Another limitation possibly hamperingimplementation of plasma dicing is that plasma processing of commonlyencountered metals (e.g., copper) in dicing along streets can createproduction issues or throughput limits.

SUMMARY

One or more embodiments of the invention are directed to methods ofdicing semiconductor wafers, each wafer having a plurality of integratedcircuits thereon. According to one embodiment, a method of dicing asemiconductor wafer including a plurality of integrated circuitsinvolves forming a mask above the semiconductor wafer. The mask coversand protects the integrated circuits. The method involves coupling thesemiconductor wafer to a film frame with an ultra-violet (UV)-curableadhesive film. The method involves pre-curing a peripheral portion ofthe adhesive film disposed beyond an edge of the semiconductor wafer.The method involves patterning the mask with a laser scribing process toprovide a patterned mask with gaps, exposing regions of thesemiconductor wafer between the integrated circuits. The method alsoinvolves etching the semiconductor wafer through the gaps in thepatterned mask to form singulated integrated circuits while thesemiconductor wafer is affixed to the adhesive film.

According to one embodiment, a method of dicing a plurality ofintegrated circuits involves coupling a masked crystalline siliconsubstrate to a film frame with a UV-curable adhesive film. The methodinvolves pre-curing a peripheral portion of the adhesive film disposedbeyond an edge of the silicon substrate. The method involves patterningthe mask, at least a layer of silicon dioxide, a layer of low Kmaterial, and a layer of copper with a laser scribing process to exposeregions of the silicon substrate between the integrated circuits. Themethod involves etching the silicon substrate through the exposedregions to form singulated integrated circuits. The method involvescuring a center portion of the adhesive film disposed within the edge ofthe silicon substrate by exposure to UV light. The method also involvesdetaching the singulated integrated circuits from the cured adhesivefilm.

According to one embodiment, a system for dicing a semiconductor wafercomprising a plurality of integrated circuits (ICs) includes adeposition chamber to form a mask above the semiconductor wafer, themask covering and protecting the ICs. The system includes an adhesivefilm applicator to couple the semiconductor wafer to a film frame withan ultra-violet (UV)-curable adhesive film. The system includes a curingstation to pre-cure a peripheral portion of the adhesive film disposedbeyond an edge of the semiconductor wafer. The system includes a laserscribe module to pattern the mask with a laser scribing process toprovide a patterned mask with gaps, exposing regions of thesemiconductor wafer between the integrated circuits. The system alsoincludes a plasma etch chamber to etch the semiconductor wafer throughthe gaps in the patterned mask to form singulated integrated circuitswhile the semiconductor wafer is affixed to the adhesive film.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are illustrated by way of example,and not limitation, in the figures of the accompanying drawings inwhich:

FIG. 1A is a flowchart representing operations in a method of dicing asemiconductor wafer including a plurality of integrated circuits, inaccordance with an embodiment of the present invention;

FIG. 1B is a flowchart representing operations in a method of dicing asemiconductor wafer including a plurality of integrated circuits, inaccordance with an embodiment of the present invention;

FIG. 2A illustrates a cross-sectional view of a semiconductor waferincluding a plurality of integrated circuits during performance of amethod of dicing the semiconductor wafer, corresponding to operation 101of FIG. 1A, in accordance with embodiments of the present invention;

FIG. 2B illustrates a cross-sectional view of a semiconductor waferincluding a plurality of integrated circuits during performance of amethod of dicing the semiconductor wafer, corresponding to operation 104of FIG. 1A and operation 115 of FIG. 1B, in accordance with embodimentsof the present invention;

FIG. 2C illustrates a cross-sectional view of a semiconductor waferincluding a plurality of integrated circuits during performance of amethod of dicing the semiconductor wafer, corresponding to operation 106of FIG. 1A and operation 116 of FIG. 1B, in accordance with embodimentsof the present invention;

FIG. 3 illustrates a cross-sectional view of a stack of materials thatmay be present in a street region of a semiconductor wafer or substrate,in accordance with embodiments of the present invention;

FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H illustrate cross-sectionalviews of various operations in a method of dicing a semiconductor wafer,in accordance with embodiments of the present invention;

FIG. 5 illustrates a block diagram of a tool layout for laser and plasmadicing of wafers or substrates, in accordance with embodiments of thepresent invention;

FIG. 6 illustrates a block diagram of an exemplary computer systemwithin which a set of instructions, for causing the computer system toperform any one or more of the methodologies discussed herein, may beexecuted.

DETAILED DESCRIPTION

Methods of dicing semiconductor wafers, each wafer having a plurality ofintegrated circuits thereon, are described. In the followingdescription, numerous specific details are set forth, such as laser andplasma etch wafer dicing approaches with UV-curable adhesive films, inorder to provide a thorough understanding of embodiments of the presentinvention. It will be apparent to one skilled in the art thatembodiments of the present invention may be practiced without thesespecific details. In other instances, well-known aspects, such asintegrated circuit fabrication, are not described in detail in order tonot unnecessarily obscure embodiments of the present invention.Furthermore, it is to be understood that the various embodiments shownin the Figures are illustrative representations and are not necessarilydrawn to scale.

A hybrid wafer or substrate dicing process involving an initial laserscribe and subsequent plasma etch may be implemented for diesingulation. The laser scribe process may be used to cleanly remove amask layer, organic and inorganic dielectric layers, and device layers.The laser scribe process may then be terminated upon exposure of, orpartial etch of, the wafer or substrate. The plasma etch portion of thedicing process may then be employed to etch through the bulk of thewafer or substrate, such as through bulk single crystalline silicon, toyield die or chip singulation or dicing.

In a hybrid wafer or substrate dicing process a wafer to be diced isgenerally mounted on a tape film frame with a UV-curable adhesive film(e.g., UV-release dicing tape). The tape film frame may be of a typeamenable to conventional pick-and-place equipment and also amenable torobotic handling and clamping inside a plasma etch chamber during thehybrid dicing process.

In an embodiment, a semiconductor wafer is mounted on a first, center,portion of an adhesive side of a single or double-side UV-curableadhesive film with a second, periphery, portion of the adhesive sideextending out beyond an edge of the wafer. Prior to loading the tapeframe into a plasma etch chamber during the plasma etching phase, a cureof the periphery portion of the adhesive side of the UV film isperformed to cross-link the adhesive in regions beyond the wafer edgethat will be exposed to the plasma etch process. It has been found thatduring plasma etching, the cured adhesive when exposed to the highdensity plasma is less subject to evaporate and redeposit into thedevice structures and etched features disposed on the wafer. Forexample, occurrences of etch stop during the plasma etch may be reducedor eliminating by the pre-curing of the periphery adhesive portion ofthe UV film.

In an embodiment, pre-curing of the periphery adhesive portion extendingbeyond the wafer edge is performed through UV irradiation from either abackside or frontside of the UV-curable adhesive film. In advantageousembodiments where the UV irradiation is performed through the backsideof the UV-curable adhesive film, a center portion of the adhesiveadhering to the wafer is shadowed from the back-side UV light with ashadow mask, for example, a dummy wafer having approximately a samediameter as the semiconductor wafer undergoing dicing.

Following the plasma etching, individual dies may be picked from theUV-curable adhesive film by curing the center portion of the adhesiveside to release the UV film. Alternatively, a second dicing tape with aframe may be applied to a front side of the semiconductor wafer and diesremoved from the UV-curable adhesive film en masse and individual diesthen picked from the taped frame for subsequent packaging and assemblyoperations.

In an embodiment, a suitable wafer thickness for the above approach isapproximately 50 microns or thicker. For IC memory chips, as memorycapacity increases, multichip functions and continuous packagingminiaturization may require ultra thin wafer dicing. For logic devicechips/processors, major challenges lie in IC performance increase, low kmaterials and other material adoption. Wafer thicknesses in the range ofapproximately 100 microns to 760 microns are used for such applicationsto ensure sufficient chip integrity. Processor chipdesigners/fabricators may place test element groups (TEGs or testpatterns) as well as alignment patterns in wafer streets. A kerf widthapproximately in the range of 50 microns to 100 microns, at least at thetop surface of the wafer, may thus be needed to separate adjacent chipsand remove only the test patterns. A major focus is to achievedelamination-free and efficient dicing processes.

Embodiments described herein may address dicing applications of ICwafers, especially with processor chips that have a thicknessapproximately in the range of 100 microns to 800 microns, and moreparticularly approximately in the range of 100 microns to 600 micronsthickness, and an acceptable dicing kerf width approximately in therange of 50 microns to 200 microns, and more particularly approximatelyin the range of 50 microns to 100 microns, measured on wafer frontsurface (e.g., corresponding typical kerf width measured from back sideof wafer is approximately 30-50 microns in a laser/saw hybrid process).One or more embodiments are directed to a hybrid laser scribing plusplasma etching approach to dice wafers as described above.

FIG. 1A illustrates operations in a method 100 of dicing a semiconductorwafer including a plurality of integrated circuits, in accordance withan embodiment of the present invention. FIG. 1B illustrates operationsin a method 140 of dicing a semiconductor wafer including a plurality ofintegrated circuits, in accordance with an embodiment of the presentinvention. Method 140 is one exemplary embodiment of the more generalmethod 100. FIGS. 2A-2C illustrate cross-sectional views of asemiconductor wafer including a plurality of integrated circuits duringperformance of the methods 100 and 140 while FIGS. 4A-4H illustratecross-sectional views of attachment and detachment of the semiconductorwafer to a carrier substrate during performance of the methods 100 and140.

Referring to operation 101 of the method 100, and corresponding FIG. 2A,a mask 202 is formed above a semiconductor wafer or substrate 204. Thewafer or substrate 204 is disposed on a UV-curable adhesive film 214having an adhesive disposed on at least one side of the carrier film.The UV-curable adhesive film 214 may be further disposed on a film frame(not shown in FIGS. 2A-2C), as described in greater detail inassociation with FIGS. 4A-4H. As is shown in FIG. 4A, a mask 410, whichmay be any of the materials described for the mask 202, is disposed onan active side 402 of semiconductor wafer 400, e.g., by spin coating aresist or other material. Although illustrated in FIG. 4A as anon-conformal, planarized mask (e.g., thickness of the mask 410 over abump is less than thickness of the mask 410 in a valley), in analternate embodiment, the mask 410 is a conformal mask. Conformal maskembodiments advantageously ensure sufficient thickness of the mask 410over topography (e.g., 20 μm bumps) to survive the duration of a plasmaetch dicing operation. Formation of a conformal mask may be by CVD, forexample, or by any other process known in the art.

Depending on the thickness or the material properties of thesemiconductor wafer 400, the mask 410 may be applied before or afterattaching the wafer 400 to a film frame. In the exemplary embodimentillustrated in FIG. 1A and FIG. 4A, the mask is applied prior toattaching the semiconductor wafer 400 to a film frame. In certain suchembodiments, the wafer 400 has a thickness greater than 350 μm. In theexemplary embodiment illustrated in FIG. 1B, the mask is appliedsubsequent to attaching the semiconductor wafer 400 to a film frame. Incertain such embodiments, the wafer 400 has a thickness less than 350μm.

As shown in FIG. 2A, the mask 202 covers and protects integratedcircuits (ICs) 206 formed on the surface of semiconductor wafer 204 andalso protects bumps projecting or protruding up (e.g., 10-20 μm) fromthe surface of the semiconductor wafer 204. The mask 202 also coversintervening streets 207 formed between adjacent ones of the integratedcircuits 206.

In accordance with an embodiment of the present invention, forming themasks 202 and 410 includes forming a layer such as, but not limited to,a photo-resist layer or an I-line patterning layer. For example, apolymer layer such as a photo-resist layer may be composed of a materialotherwise suitable for use in a lithographic process. In one embodiment,the photo-resist layer is composed of a positive photo-resist materialsuch as, but not limited to, a 248 nanometer (nm) resist, a 193 nmresist, a 157 nm resist, an extreme ultra-violet (EUV) resist, or aphenolic resin matrix with a sensitizer. In another embodiment, thephoto-resist layer is composed of a negative photo-resist material.

In an embodiment, semiconductor wafer or substrates 204 (FIGS. 2A-2C)and 400 (FIG. 4A-4G) are of a material suitable to withstand afabrication process and upon which semiconductor processing layers maysuitably be disposed. For example, in one embodiment, semiconductorwafer or substrate 204 is composed of a group IV-based material such as,but not limited to, crystalline silicon, germanium or silicon/germanium.In a specific embodiment, providing semiconductor wafer 204 includesproviding a monocrystalline silicon substrate. In a particularembodiment, the monocrystalline silicon substrate is doped with impurityatoms. In another embodiment, semiconductor wafer or substrate 204 iscomposed of a III-V material or III-N such as, e.g., GaN used in thefabrication of light emitting diodes (LEDs).

Referring to FIG. 2A, the semiconductor wafer or substrate 204 hasdisposed thereon or therein, as a portion of the integrated circuits206, an array of semiconductor devices. Examples of such semiconductordevices include, but are not limited to, memory devices or complimentarymetal-oxide-semiconductor (CMOS) transistors fabricated in a siliconsubstrate and encased in a dielectric layer. A plurality of metalinterconnects may be formed above the devices or transistors, and insurrounding dielectric layers, and may be used to electrically couplethe devices or transistors to form the integrated circuits 206.Conductive bumps and passivation layers may be formed above theinterconnect layers. Materials making up the streets 207 may be similarto or the same as those materials used to form the integrated circuits206. For example, the streets 207 may be composed of layers ofdielectric materials, semiconductor materials, and metallization. In oneembodiment, one or more of the streets 207 includes test devices similarto the actual devices of the integrated circuits 206.

Returning to FIG. 1A, the method 100 proceeds with coupling asemiconductor wafer to a film frame with a UV-curable adhesive film atoperation 102. In an embodiment, the UV-curable adhesive film 214 inFIGS. 2A-2C and the UV-curable adhesive film 406 in FIGS. 4B-4H is adicing tape including a carrier film disposed under at least a firstadhesive layer or side (a second adhesive layer may be present on anopposite side of the carrier film for double-sided embodiments). In anembodiment, the adhesive is composed of a material, or materials, withan adhesive property that weakens (i.e., releases) upon exposure to UVlight. In one such embodiment, the carrier film is composed of polyvinylchloride and the one or two adhesive layers are acrylic-based adhesivelayers.

In one embodiment, as shown in FIG. 4B, coupling the wafer to theadhesive film entails contacting one adhesive layer 404A to the filmframe 408. In the embodiment illustrated, the UV-cureable adhesive filmis applied, for example with a conventional wafer tape applicator, firstto the film frame 408 and then a second adhesive layer or side 404B iscontacted to the semiconductor wafer 400 (FIG. 4B). Because the filmframe 408 is larger than the wafer (e.g., ˜380 mm for a 300 mm diameterwafer), the wafer 400 may be aligned to the taped film frame 408 beforecontacting the exposed adhesive. In an alternative embodiment, theUV-cureable adhesive film is applied, for example with a conventionalwafer tape applicator, first to the semiconductor wafer 400, beforecontacting a second adhesive side to the film frame 408. For suchembodiments, a first side of the double-side UV-curable tape is appliedto the wafer backside (opposite front side 402), the taped wafer is thenaligned with an untaped film frame and brought into contact with thefilm frame.

As shown in FIG. 4C, with the adhesive film 406 applied to a side of thefilm frame 408 by way of the adhesive layer 404A, the semiconductorwafer 400 is affixed to the other adhesive layer 404B with the mask 410exposed. Although it is advantageous to apply the adhesive to thecarrier substrate first where the semiconductor wafer 400 is veryfragile, in alternate embodiments the double-sided adhesive film 406(e.g., adhesive layer 404B) may also be applied to the wafer 400 firstand then the other side of the adhesive film (e.g., adhesive layer 404A)applied to the film frame 408.

Returning to FIG. 1A, with the semiconductor wafer mounted onto thecarrier, method 100 proceeds to operation 103 with the maskedsemiconductor wafer coupled to a film frame with UV-curable adhesivefilm. Similarly, method 140 (FIG. 1B) begins with operation 113, forexample taking as an input starting material the assembly thus farprepared by method 100. Both the methods 100 and 140 then proceed withpre-curing of a peripheral portion of adhesive extending beyond thewafer edge on the same side of the carrier film as the wafer. In otherwords, the adhesive layer not contacted by the wafer and exposed on thewafer-side beyond the wafer edge is pre-cured. The pre-cure operations(103, 114) are to cross-link the adhesive material that will be exposedto the plasma during a subsequent plasma etch phase of the scribingprocess. Once cross-linked, the adhesive material becomes more etchresistant and less prone to spawning hydrocarbons subject toredeposition during the etch process. As such redeposition has beenfound to adversely affect etch performance, potentially contributing toone or more of: etch stop, chamber or wafer contamination, or loss ofetch profile control, the pre-curing operation (e.g., 103 in FIG. 1A,114 in FIG. 1B) has been found advantageous.

In one embodiment illustrated in FIG. 4C, the pre-cure operation entailsexposing a top side adhesive to UV light originating from a back side ofthe adhesive film 406 and/or back side of the wafer 400. As such, atleast some portion of the UV light transmits or passes through thecarrier film of the adhesive film 406 before interacting with the top(front) side adhesive during the pre-curing. Although, in an alternateembodiment UV light originating from a front (top) side of the adhesivefilm 406 and/or front (top) side of the wafer 400 is utilized during thepre-curing operation, backside UV exposure has been found to be acleaner process, minimizing the potential for particle adders and othercontamination associated with front side processing. As further shown inFIG. 4C, the peripheral region 414 of the adhesive, beyond the perimeterwafer edge 400A, is irradiated while a mask 405 protects a centerportion of the adhesive from being cured during the pre-cure. Generally,the mask 405 may be any contact or projection shadow mask capable ofserving as a UV barrier to prevent curing of the adhesive disposedbetween the wafer 400 and the mask 405. In one embodiment, the mask 405is approximately the same size as the wafer 400 and may be a dummywafer, such as, but not limited to a silicon semiconductor wafer havinga same diameter (e.g., 300 mm, 450 mm, etc.) as the wafer 400. The mask405 is generally aligned with the wafer 400 during the pre-cureoperation although some misregistration is acceptable as there istypically an edge bead exclusion on the wafer 400 which may loseadhesion after dicing as a result of the pre-etch partial cure withoutincurring die yield loss.

Following the pre-cure, the methods 100 and 140 proceed with laserscribe operations (104 and 115) and plasma etch operations (106 and116). FIG. 2B provides a proximal cross-sectional view of the mask 202being patterned with a laser scribing process to provide a patternedmask 208 with gaps 210, exposing regions of the semiconductor wafer orsubstrate 204 between the integrated circuits 206. FIG. 4D provides adistal cross-section view of the laser scribe process forming the gaps412 while the wafer 400 is affixed to the film frame 408 by adhesivefilm 406.

Referring to FIG. 2B, the laser scribing process is generally to removethe material of the streets 207 present between the integrated circuits206. In accordance with an embodiment of the present invention,patterning the mask 202 with the laser scribing process includes formingtrenches 212 partially into the regions of the semiconductor wafer 204between the integrated circuits 206. In an embodiment, patterning themask 202 with the laser scribing process includes using a laser having apulse width in the femtosecond range. Specifically, a laser with awavelength in the visible spectrum or the ultra-violet (UV) or infra-red(IR) ranges (the three totaling a broadband optical spectrum) may beused to provide a femtosecond-based laser, i.e., a laser with a pulsewidth on the order of the femtosecond (10⁻¹⁵ seconds). In oneembodiment, ablation is not, or is essentially not, wavelength dependentand is thus suitable for complex films such as films of the mask 202,the streets 207 and, possibly, a portion of the semiconductor wafer orsubstrate 204.

Laser parameters selection, such as pulse width, may be critical todeveloping a successful laser scribing and dicing process that minimizeschipping, microcracks and delamination in order to achieve clean laserscribe cuts. The cleaner the laser scribe cut, the smoother an etchprocess that may be performed for ultimate die singulation. Insemiconductor device wafers, many functional layers of differentmaterial types (e.g., conductors, insulators, semiconductors) andthicknesses are typically disposed thereon. Such materials may include,but are not limited to, organic materials such as polymers, metals, orinorganic dielectrics such as silicon dioxide and silicon nitride.

A street between individual integrated circuits disposed on a wafer orsubstrate may include the similar or same layers as the integratedcircuits themselves. For example, FIG. 3 illustrates a cross-sectionalview of a stack of materials that may be used in a street region of asemiconductor wafer or substrate, in accordance with an embodiment ofthe present invention. Referring to FIG. 3, a street region 300 includesthe top portion 302 of a silicon substrate, a first silicon dioxidelayer 304, a first etch stop layer 306, a first low K dielectric layer308 (e.g., having a dielectric constant of less than the dielectricconstant of 4.0 for silicon dioxide), a second etch stop layer 310, asecond low K dielectric layer 312, a third etch stop layer 314, anundoped silica glass (USG) layer 316, a second silicon dioxide layer318, and a layer of photo-resist 320, with relative thicknessesdepicted. Copper metallization 322 is disposed between the first andthird etch stop layers 306 and 314 and through the second etch stoplayer 310. In a specific embodiment, the first, second and third etchstop layers 306, 310 and 314 are composed of silicon nitride, while lowK dielectric layers 308 and 312 are composed of a carbon-doped siliconoxide material.

Under conventional laser irradiation (such as nanosecond-based orpicosecond-based laser irradiation), the materials of street 300 maybehave quite differently in terms of optical absorption and ablationmechanisms. For example, dielectrics layers such as silicon dioxide, isessentially transparent to all commercially available laser wavelengthsunder normal conditions. By contrast, metals, organics (e.g., low Kmaterials) and silicon can couple photons very easily, particularly inresponse to nanosecond-based or picosecond-based laser irradiation. Inan embodiment, however, a femtosecond-based laser process is used topattern a layer of silicon dioxide, a layer of low K material, and alayer of copper by ablating the layer of silicon dioxide prior toablating the layer of low K material and the layer of copper. In aspecific embodiment, pulses of approximately less than or equal to 400femtoseconds are used in a femtosecond-based laser irradiation processto remove a mask, a street, and a portion of a silicon substrate.

In accordance with an embodiment of the present invention, suitablefemtosecond-based laser processes are characterized by a high peakintensity (irradiance) that usually leads to nonlinear interactions invarious materials. In one such embodiment, the femtosecond laser sourceshave a pulse width approximately in the range of 10 femtoseconds to 500femtoseconds, although preferably in the range of 100 femtoseconds to400 femtoseconds. In one embodiment, the femtosecond laser sources havea wavelength approximately in the range of 1570 nanometers to 200nanometers, although preferably in the range of 540 nanometers to 250nanometers. In one embodiment, the laser and corresponding opticalsystem provide a focal spot at the work surface approximately in therange of 3 microns to 15 microns, though preferably approximately in therange of 5 microns to 10 microns.

The spacial beam profile at the work surface may be a single mode(Gaussian) or have a shaped top-hat profile. In an embodiment, the lasersource has a pulse repetition rate approximately in the range of 200 kHzto 10 MHz, although preferably approximately in the range of 500 kHz to5 MHz. In an embodiment, the laser source delivers pulse energy at thework surface approximately in the range of 0.5 μJ to 100 μJ, althoughpreferably approximately in the range of 1 μJ to 5 μJ. In an embodiment,the laser scribing process runs along a work piece surface at a speedapproximately in the range of 500 mm/sec to 5 m/sec, although preferablyapproximately in the range of 600 mm/sec to 2 m/sec.

The scribing process may be run in single pass only, or in multiplepasses, but, in an embodiment, preferably 1-2 passes. In one embodiment,the scribing depth in the work piece is approximately in the range of 5microns to 50 microns deep, preferably approximately in the range of 10microns to 20 microns deep. The laser may be applied either in a trainof single pulses at a given pulse repetition rate or a train of pulsebursts. In an embodiment, the kerf width of the laser beam generated isapproximately in the range of 2 microns to 15 microns, although insilicon wafer scribing/dicing preferably approximately in the range of 6microns to 10 microns, measured at the device/silicon interface.

Laser parameters may be selected with benefits and advantages such asproviding sufficiently high laser intensity to achieve ionization ofinorganic dielectrics (e.g., silicon dioxide) and to minimizedelamination and chipping caused by underlayer damage prior to directablation of inorganic dielectrics. Also, parameters may be selected toprovide meaningful process throughput for industrial applications withprecisely controlled ablation width (e.g., kerf width) and depth. Asdescribed above, a femtosecond-based laser is far more suitable toproviding such advantages, as compared with picosecond-based andnanosecond-based laser ablation processes. However, even in the spectrumof femtosecond-based laser ablation, certain wavelengths may providebetter performance than others. For example, in one embodiment, afemtosecond-based laser process having a wavelength closer to or in theUV range provides a cleaner ablation process than a femtosecond-basedlaser process having a wavelength closer to or in the IR range. In aspecific such embodiment, a femtosecond-based laser process suitable forsemiconductor wafer or substrate scribing is based on a laser having awavelength of approximately less than or equal to 540 nanometers. In aparticular such embodiment, pulses of approximately less than or equalto 400 femtoseconds of the laser having the wavelength of approximatelyless than or equal to 540 nanometers are used. However, in analternative embodiment, dual laser wavelengths (e.g., a combination ofan IR laser and a UV laser) are used.

Returning to FIGS. 1A and 1B, at the plasma etch operations (106, 116),the semiconductor wafer is plasma etched to singulate the ICs. Theplasma etch front proceeds through the gaps 210 in the patterned mask208 to form singulated integrated circuits 206. In accordance with anembodiment of the present invention, etching the semiconductor waferincludes etching the trenches formed with the laser scribing process toultimately etch entirely through semiconductor wafer. This isillustrated both in FIG. 2C for the substrate 204 and in FIG. 4E for thewafer 400 (with formation of the through trench 416). In the exemplaryembodiments illustrated by FIGS. 2C and 4E, the plasma etch is stoppedon the adhesive film 214, 406, respectively with individualized portions414 (e.g., 414A and 414B) of the semiconductor wafer 400 separated bytrench 416.

As illustrated in FIG. 4E, during the plasma etch process, the wafer 400is disposed on a chuck 508A while attached to the film frame by theadhesive film. The film frame 408 being lager than the chuck 508A restson an outer ring 508B surrounding the chuck 508A. In a specificembodiment, during the etch process the etch rate of the material ofsemiconductor wafer 400 is greater than 25 microns per minute. Anultra-high-density plasma source may be used for the plasma etchingportion of the die singulation process. An example of a process chambersuitable to perform such a plasma etch process is the Applied Centura®Silvia™ Etch system available from Applied Materials of Sunnyvale,Calif., USA. The Applied Centura® Silvia™ Etch system combines thecapacitive and inductive RF coupling, which gives much more independentcontrol of the ion density and ion energy than is possible withcapacitive coupling only, even with the improvements provided bymagnetic enhancement. This combination enables effective decoupling ofthe ion density from ion energy, so as to achieve relatively highdensity plasmas without the high, potentially damaging, DC bias levels,even at very low pressures. Multi-RF source configurations also resultsin an exceptionally wide process window. However, any plasma etchchamber capable of etching silicon may be used. In an exemplaryembodiment, a deep silicon etch is used to etch a single crystallinesilicon substrate or wafer 204 at an etch rate greater thanapproximately 40% of conventional silicon etch rates (e.g., 40 μm, ormore) while maintaining essentially precise profile control andvirtually scallop-free sidewalls. In a specific embodiment, athrough-silicon via type etch process is used. The etch process is basedon a plasma generated from a reactive gas, which generally is afluorine-based gas such as SF₆, C₄F₈, CHF₃, XeF₂, or any other reactantgas capable of etching silicon at a relatively fast etch rate.

Following the plasma etch operation (106 in FIG. 1A and 116 in FIG. 1B),the singulated integrated circuits remain coupled to the UV-curableadhesive film. Referring to FIG. 1A, at operation 108, and described ingreater detail below in association with FIGS. 4F-4H, a center portionof the UV-curable adhesive film is cured with UV (light) energyirradiation to weaken the adhesive properties the of the UV-curableadhesive affixed to the wafer. In the exemplary embodiment illustratedby FIG. 4F, the patterned mask 410 of FIGS. 4A-4E is removed after thelaser scribe and plasma etch portions of the singulation process andbefore removal of the adhesive film 406. This is also depicted by FIG.2C. However, in alternate embodiments, the patterned mask 208 may beremoved during, or following the second UV irradiation of the UV-curableadhesive film to which the center portion of the adhesive is exposed.

As illustrated by FIG. 4G, the UV-curable adhesive film is re-irradiatedwith UV light 420 through the film frame 408 in the absence of any mask(i.e., mask 405 of FIG. 4C has been removed). The UV light 420 is alsotransmitted through the carrier film of the UV-curable adhesive film inthe center region 417 disposed below the wafer 400 to release theindividualized ICs 415A, 415B from the adhesive tape. For example, as inoperation 117 in method 140 (FIG. 1B), there is a complete cure of theadhesive side in contact with the wafer where curing a UV-releaseadhesive entails reducing an adhesiveness of one side of UV-curableadhesive film by at least 90%.

As further illustrated in FIG. 4H, with neither the pre-cure nor thesecondary adhesive cure occurring from a top side of the wafer 400 (orframe 408) the adhesive film may be preferentially retained on the filmframe when individualized ICs 415A, 415B are detached from the adhesivefilm and/or film frame 408. Notably, the operations 108 and 110 (or 117and 121) may be performed at a package assembly house after a dicedwafer is transported on the film frame from a IC fabrication facility,for example. The package assembly house may thereby utilize the filmframe 408 much as they would any tape frame in a conventional pick andplace packaging process. In one such embodiment, for example asillustrated by operation 121 in method 140 (FIG. 1B), detachment of dieis on an individual die-basis with a conventional pick-n-place machine.

Alternatively, a protective layer, such as a conventional protectivedicing tape may be applied to the side opposite the UV adhesive film406, for example as would be done to a side of the semiconductor priorto dicing in conventional dicing tape/tape frame application. Once afront-side dicing tape was applied, the UV-curable adhesive film 406 maybe partially cured to release the wafer side of the UV-curable adhesivefilm 406 as the front-side tape is expanded onto a tape frame. In suchembodiments, the individualized die including ICs 415A and 415B aredetached from the UV-curable adhesive film 406 at the wafer level.

Referring again to FIGS. 2A-2C, the plurality of integrated circuits 206may be separated by streets 207 having a width of approximately 10microns or smaller. The use of a femtosecond-based laser scribingapproach, at least in part due to the tight profile control of thelaser, may enable such compaction in a layout of integrated circuits. Itis to be understood, however, that it may not always be desirable toreduce the street width to less than 10 microns even if otherwiseenabled by a femtosecond-based laser scribing process. For example, someapplications may require a street width of at least 40 microns in orderto fabricate dummy or test devices in the streets separating theintegrated circuits. In an embodiment, the plurality of integratedcircuits 206 may be arranged on semiconductor wafer or substrate 204 ina non-restricted or freeform layout.

A single process tool may be configured to perform many or all of theoperations in a hybrid laser ablation and plasma etch singulationprocess including the use of a UV-curable adhesive film. For example,FIG. 5 illustrates a block diagram of a tool layout for laser and plasmadicing of wafers or substrates, in accordance with an embodiment of thepresent invention.

Referring to FIG. 5, a process tool 500 includes a factory interface 502(FI) having a plurality of load locks 504 coupled therewith. A clustertool 506 is coupled with the factory interface 502. The cluster tool 506includes a plasma etch chamber 508. A laser scribe apparatus 510 is alsocoupled to the factory interface 502. The overall footprint of theprocess tool 500 may be, in one embodiment, approximately 3500millimeters (3.5 meters) by approximately 3800 millimeters (3.8 meters),as depicted in FIG. 5.

In an embodiment, the laser scribe apparatus 510 houses a laser. In onesuch embodiment, the laser is a femtosecond-based laser. The laser issuitable for performing a laser ablation portion of a hybrid laser andetch singulation process including the use of a mask, such as the laserablation processes described above. In one embodiment, a moveable stageis also included in process tool 500, the moveable stage configured formoving a wafer or substrate (or a carrier thereof) relative to thelaser. In a specific embodiment, the laser is also moveable. The overallfootprint of the laser scribe apparatus 510 may be, in one embodiment,approximately 2240 millimeters by approximately 1270 millimeters, asdepicted in FIG. 5.

In an embodiment, the plasma etch chamber 508 is configured for etchinga wafer or substrate through the gaps in a patterned mask to singulate aplurality of integrated circuits. In one such embodiment, the plasmaetch chamber 508 is configured to perform a deep silicon etch process.In a specific embodiment, the plasma etch chamber 508 is an AppliedCentura® Silvia™ Etch system, available from Applied Materials ofSunnyvale, Calif., USA. The plasma etch chamber 508 may be specificallydesigned for a deep silicon etch used to singulate integrated circuitshoused on or in single crystalline silicon substrates or wafers. In anembodiment, a high-density plasma source is included in the plasma etchchamber 508 to facilitate high silicon etch rates. In an embodiment,more than one plasma etch chamber is included in the cluster tool 506portion of process tool 500 to enable high manufacturing throughput ofthe singulation or dicing process.

In an embodiment, the plasma etch chamber 508 includes a chuck disposedwithin the chamber to clamp a wafer while disposed on a tape frameduring a plasma process. The factory interface 502 may be a suitableatmospheric port to interface between an outside manufacturing facilitywith laser scribe apparatus 510 and cluster tool 506. The factoryinterface 502 may include robots with arms or blades for transferringwafers (or carriers thereof) from storage units (such as front openingunified pods) into either cluster tool 506 or laser scribe apparatus510, or both.

Cluster tool 506 may include other chambers suitable for performingfunctions in a method of singulation. For example, in one embodiment, inplace of an additional etch chamber, a deposition chamber 512 isincluded. The deposition chamber 512 may be configured for maskdeposition on or above a device layer of a wafer or substrate prior tolaser scribing of the wafer or substrate. In one such embodiment, thedeposition chamber 512 is suitable for depositing a photo-resist layer.

FIG. 6 illustrates a computer system 600 within which a set ofinstructions, for causing the machine to execute one or more of thescribing methods discussed herein may be executed. The exemplarycomputer system 600 includes a processor 602, a main memory 604 (e.g.,read-only memory (ROM), flash memory, dynamic random access memory(DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), astatic memory 606 (e.g., flash memory, static random access memory(SRAM), etc.), and a secondary memory 618 (e.g., a data storage device),which communicate with each other via a bus 630.

Processor 602 represents one or more general-purpose processing devicessuch as a microprocessor, central processing unit, or the like. Moreparticularly, the processor 602 may be a complex instruction setcomputing (CISC) microprocessor, reduced instruction set computing(RISC) microprocessor, very long instruction word (VLIW) microprocessor,etc. Processor 602 may also be one or more special-purpose processingdevices such as an application specific integrated circuit (ASIC), afield programmable gate array (FPGA), a digital signal processor (DSP),network processor, or the like. Processor 602 is configured to executethe processing logic 626 for performing the operations and stepsdiscussed herein.

The computer system 600 may further include a network interface device608. The computer system 600 also may include a video display unit 610(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), analphanumeric input device 612 (e.g., a keyboard), a cursor controldevice 614 (e.g., a mouse), and a signal generation device 616 (e.g., aspeaker).

The secondary memory 618 may include a machine-accessible storage medium(or more specifically a computer-readable storage medium) 631 on whichis stored one or more sets of instructions (e.g., software 622)embodying any one or more of the methodologies or functions describedherein. The software 622 may also reside, completely or at leastpartially, within the main memory 604 and/or within the processor 602during execution thereof by the computer system 600, the main memory 604and the processor 602 also constituting machine-readable storage media.The software 622 may further be transmitted or received over a network620 via the network interface device 608.

While the machine-accessible storage medium 631 is shown in an exemplaryembodiment to be a single medium, the term “machine-readable storagemedium” should be taken to include a single medium or multiple media(e.g., a centralized or distributed database, and/or associated cachesand servers) that store the one or more sets of instructions. The term“machine-readable storage medium” shall also be taken to include anymedium that is capable of storing or encoding a set of instructions forexecution by the machine and that cause the machine to perform any oneor more of the methodologies of the present invention.

For example, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium (e.g.,read only memory (“ROM”), random access memory (“RAM”), magnetic diskstorage media, optical storage media, flash memory devices, etc.), amachine (e.g., computer) readable transmission medium (electrical,optical, acoustical or other form of propagated signals (e.g., infraredsignals, digital signals, etc.)), etc.

It is to be understood that the above description is intended to beillustrative, and not restrictive. For example, while flow diagrams inthe figures show a particular order of operations performed by certainembodiments of the invention, it should be understood that such order isnot required (e.g., alternative embodiments may perform the operationsin a different order, combine certain operations, overlap certainoperations, etc.). Furthermore, many other embodiments will be apparentto those of skill in the art upon reading and understanding the abovedescription. Although the present invention has been described withreference to specific exemplary embodiments, it will be recognized thatthe invention is not limited to the embodiments described, but can bepracticed with modification and alteration within the spirit and scopeof the appended claims. The scope of the invention should, therefore, bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

What is claimed is:
 1. A method of dicing a semiconductor wafercomprising a plurality of integrated circuits, the method comprising:forming a mask above the semiconductor wafer, the mask covering andprotecting the integrated circuits; coupling the semiconductor wafer toa film frame with an ultra-violet (UV)-curable adhesive film; pre-curinga peripheral portion of the adhesive film disposed beyond an edge of thesemiconductor wafer; patterning the mask with a laser scribing processto provide a patterned mask with gaps, exposing regions of thesemiconductor wafer between the integrated circuits; and etching thesemiconductor wafer through the gaps in the patterned mask to formsingulated integrated circuits while the semiconductor wafer is affixedto the adhesive film.
 2. The method of claim 1, wherein the adhesivefilm is transmissive of UV light and wherein the pre-curing furthercomprises: irradiating the peripheral portion of the adhesive film withUV light originating from a backside of the adhesive film, at least someof the UV light passing through the adhesive film on which theperipheral portion of the adhesive film is disposed before etching thesemiconductor wafer.
 3. The method of claim 2, wherein the pre-curingfurther comprises: masking a center portion of the adhesive film toprotect the center portion from UV exposure during the pre-curing of theperipheral portion.
 4. The method of claim 3, wherein masking the centerportion further comprises disposing a UV barrier having a dimensionapproximately equal to that of the semiconductor wafer adjacent to thebackside of the adhesive film in alignment with the semiconductor wafer.5. The method of claim 4, wherein the UV barrier further comprises adummy wafer of a same diameter as the semiconductor wafer.
 6. The methodof claim 5, wherein the semiconductor wafer and the dummy wafer aresilicon, have a thickness approximately in a range of 100-600 μm, andare between 300 and 450 mm in diameter.
 7. The method of claim 1,further comprising: curing a center portion of the adhesive filmdisposed within the edge of the semiconductor wafer by exposure to UVlight; and detaching the singulated integrated circuits from the curedadhesive film.
 8. The method of claim 2, wherein the UV-curable adhesivefilm comprises at least one acrylic-based adhesive disposed on apolyvinyl chloride film.
 9. The method of claim 2, wherein coupling thesemiconductor wafer to a film frame with an ultra-violet (UV)-curableadhesive film further comprises: contacting the adhesive film to thefilm frame; aligning the semiconductor wafer to the film frame; andcontacting the semiconductor wafer to the adhesive film.
 10. The methodof claim 1, wherein patterning the mask with the laser scribing processcomprises patterning with a femtosecond-based laser scribing process,and wherein etching the semiconductor wafer through the gaps in thepatterned mask comprises using a high density plasma etching process.11. The method of claim 9, wherein using a high density plasma etchingprocess comprises: disposing the film frame on a support surrounding achuck disposed in an etch process chamber; clamping the semiconductorwafer to the chuck; plasma etching the semiconductor wafer through thegaps in the patterned mask while disposed on the chuck; and unclampingthe semiconductor wafer.
 12. A method of dicing a plurality ofintegrated circuits, the method comprising: coupling a maskedcrystalline silicon substrate to a film frame with a UV-curable adhesivefilm, a mask covering and protecting integrated circuits disposed on thesilicon substrate; pre-curing a peripheral portion of the adhesive filmdisposed beyond an edge of the silicon substrate; patterning the mask,at least a layer of silicon dioxide, a layer of low K material, and alayer of copper with a laser scribing process to expose regions of thesilicon substrate between the integrated circuits; etching the siliconsubstrate through the exposed regions to form singulated integratedcircuits; curing a center portion of the adhesive film disposed withinthe edge of the silicon substrate by exposure to UV light; and detachingthe singulated integrated circuits from the cured adhesive film.
 13. Themethod of claim 12, further comprising forming the mask above thesilicon substrate before the silicon substrate is coupled to the filmframe.
 14. The method of claim 12, wherein the adhesive film istransmissive of UV light, and wherein the pre-curing further comprises:masking the center portion of the adhesive film to protect the centerportion from UV exposure; and irradiating the peripheral portion of theadhesive film with UV light originating from a backside of the adhesivefilm, at least some of the UV light passing through the adhesive film onwhich the peripheral portion of the adhesive film is disposed beforeetching the silicon substrate.
 15. The method of claim 14, furthercomprising: re-irradiating the UV-curable adhesive film with UV lightoriginating from the backside of the adhesive film, curing the centerportion of the adhesive film disposed within the edge of the siliconsubstrate.
 16. The method of claim 15, further comprising: subsequent toetching the silicon substrate and prior to re-irradiating the UV-curableadhesive film, removing the mask.
 17. The method of claim 12, whereinpatterning the mask, the layer of silicon dioxide, the layer of low Kmaterial, and the layer of copper with the laser scribing processcomprises patterning with a femtosecond-based laser scribing process,and wherein etching the silicon substrate through the exposed regionscomprises using a high density plasma etching process.
 18. A system fordicing a semiconductor wafer comprising a plurality of integratedcircuits (ICs), the system comprising: a deposition chamber to form amask above the semiconductor wafer, the mask covering and protecting theICs; an adhesive film applicator to couple the semiconductor wafer to afilm frame with an ultra-violet (UV)-curable adhesive film; a curingstation to pre-cure a peripheral portion of the adhesive film disposedbeyond an edge of the semiconductor wafer; a laser scribe module topattern the mask with a laser scribing process to provide a patternedmask with gaps, exposing regions of the semiconductor wafer between theintegrated circuits; and a plasma etch chamber to etch the semiconductorwafer through the gaps in the patterned mask to form singulatedintegrated circuits while the semiconductor wafer is affixed to theadhesive film.
 19. The system of claim 18, wherein the curing station isto irradiate the peripheral portion of the adhesive film with UV lightoriginating from a backside of the adhesive film, at least some of theUV light passing through the adhesive film on which the peripheralportion of the adhesive film is disposed before etching thesemiconductor wafer.
 20. The system of claim 18, wherein the curingstation is to further mask a center portion of the adhesive film toprotect the center portion from UV exposure during the pre-curing of theperipheral portion.